1. Field of the Invention
The present invention relates to a semiconductor device and a method of manufacturing it, and more particularly to LD (Lateral Double Diffused) MOS transistor technology which is used for a high voltage element for e.g. liquid crystal driving IC.
2. Description of the Related Art
Now, an LDMOS transistor structure refers to a structure in which impurities with a different conduction type are diffused in a diffused region formed on surface of a semiconductor substrate to form another diffused region and a difference in the horizontal diffusion between these diffused regions is employed as an effective channel length. This structure, in which a short channel is formed, can constitute an element with low "on" resistance.
FIGS. 11A and 11B are a sectional view for explaining a conventional LDMOS transistor. A N-channel LDMOS transistor structure is illustrated. Although the structure of a P-channel LDMOS transistor structure is not explained here, it is well known that the same structure can be adopted except for its conduction type.
In FIG. 10A, reference numeral 1 denotes a semiconductor substrate with a first conduction type, e.g. P-type, and reference numeral 2 denotes a P-type well region. A P-type body region 3 is formed within the P-type well region 1. An N-type diffused region 4 is formed within the P-type body region 3. Another N-type diffused region 5 is formed apart from the N-type diffused region 4. A gate electrode 7 is formed on the surface of the substrate 1 through a gate insulating film 6. A channel region 8 is formed in the surface region of the P-type body region 3 immediately below the gate electrode.
The N-type diffused region 4 is used as a source region whereas the N-type diffused region is used as a drain region. The N-type well region 2 below a LOCOS oxide film 9 is used as a drift region. Further, reference numerals 10 and 11 denote a source electrode and drain electrode, respectively. Reference numeral 12 denotes a P-type diffused region for assuming the potential of the P-type body region 3 and reference numeral 13 denotes an interlayer insulating film.
In the above LDMOS transistor, since the N-type well region 2 is formed by diffusion, a high impurity concentration is given on the surface of the N-type well region, a current is apt to flow in the surface of the N-type well region, thereby realizing a high withstand voltage. The LDMOS transistor having such a configuration is referred to as a surface relax type (RESURF)LDMOS. The dopant concentration of the drift region in the N-type well region 2 is set so as to satisfy the condition of RESURF. Such a technique is disclosed in JP-A-9-139438.
However, since the impurity concentration is high in the surface of the N-type well region, P-type impurity for forming the P-type body region 3 cannot diffuse sufficiently. Therefore, as shown in FIG. 11B, the edge of the P-type body region 3 approaches the source region (N-type diffused region 4) so that the channel region 8 may be not be formed to have a suitable size (see indicated arrow A).